APA (7th ed.) Citation

Taraate, V. (2016). Digital Logic Design Using Verilog: Coding and RTL Synthesis (1st ed. 2016.). Springer India. https://doi.org/10.1007/978-81-322-2791-5

Chicago Style (17th ed.) Citation

Taraate, Vaibbhav. Digital Logic Design Using Verilog: Coding and RTL Synthesis. 1st ed. 2016. New Delhi: Springer India, 2016. https://doi.org/10.1007/978-81-322-2791-5.

MLA (9th ed.) Citation

Taraate, Vaibbhav. Digital Logic Design Using Verilog: Coding and RTL Synthesis. 1st ed. 2016. Springer India, 2016. https://doi.org/10.1007/978-81-322-2791-5.