APA (7th ed.) Citation

Lourenço, N., Martins, R., & Horta, N. (2017). Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects (1st ed. 2017.). Springer International Publishing : Imprint: Springer. https://doi.org/10.1007/978-3-319-42037-0

Chicago Style (17th ed.) Citation

Lourenço, Nuno, Ricardo Martins, and Nuno Horta. Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects. 1st ed. 2017. Cham: Springer International Publishing : Imprint: Springer, 2017. https://doi.org/10.1007/978-3-319-42037-0.

MLA (9th ed.) Citation

Lourenço, Nuno, et al. Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects. 1st ed. 2017. Springer International Publishing : Imprint: Springer, 2017. https://doi.org/10.1007/978-3-319-42037-0.