Formal Verification of Simulink/Stateflow Diagrams A Deductive Approach /

This book presents a state-of-the-art technique for formal verification of continuous-time Simulink/Stateflow diagrams, featuring an expressive hybrid system modelling language, a powerful specification logic and deduction-based verification approach, and some impressive, realistic case studies. Rea...

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Detaylı Bibliyografya
Asıl Yazarlar: Zhan, Naijun (Yazar), Wang, Shuling (Yazar), Zhao, Hengjun (Yazar)
Müşterek Yazar: SpringerLink (Online service)
Materyal Türü: e-Kitap
Dil:İngilizce
Baskı/Yayın Bilgisi: Cham : Springer International Publishing : 2017.
Imprint: Springer,
Edisyon:1st ed. 2017.
Konular:
Electronic circuits.
Microprocessors.
Computer architecture.
Electronic Circuits and Systems.
Processor Architectures.
Online Erişim:Full-text access
Diğer Bilgiler
Özet:This book presents a state-of-the-art technique for formal verification of continuous-time Simulink/Stateflow diagrams, featuring an expressive hybrid system modelling language, a powerful specification logic and deduction-based verification approach, and some impressive, realistic case studies. Readers will learn the HCSP/HHL-based deductive method and the use of corresponding tools for formal verification of Simulink/Stateflow diagrams. They will also gain some basic ideas about fundamental elements of formal methods such as formal syntax and semantics, and especially the common techniques applied in formal modelling and verification of hybrid systems. By investigating the successful case studies, readers will realize how to apply the pure theory and techniques to real applications, and hopefully will be inspired to start to use the proposed approach, or even develop their own formal methods in their future work.
Fiziksel Özellikler:XV, 258 p. 74 illus., 60 illus. in color. online resource.
ISBN:9783319470160
DOI:10.1007/978-3-319-47016-0

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