Arama Sonuçları - "Arithmetic logic unit"

Memristor-Based Nanoelectronic Computing Circuits and Architectures Foreword by Leon Chua / Yazar: Vourkas, Ioannis, Sirakoulis, Georgios Ch

İçindekiler: “…Memristor Fundamentals -- Memristor Modeling -- Dynamic Response of Multiple Interconnected Memristors -- Memristor-based Logic Circuits -- Memristive Crossbar-based Nonvolatile Memory -- High-radix Arithmetic-Logic Unit (ALU) Based on Memristors -- Networks of Memristors and Memristive Components -- Memristive Computing for NP-Hard AI Problems.…”
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Nanoelectronic Materials and Devices Select Proceedings of ICNETS2, Volume III /

İçindekiler: “…The Effect of Functionalized MWCNT on Mechanical and Electrical Properties of PMMA Nanocomposites -- Performance Analysis of Dual-Metal Double-Gate Tunnel-Fets for Ultralow Power Applications -- Films of Reduced Graphene Oxide based Metal Oxide Nanoparticles -- Size optimization of InAs/GaAs quantum dots for longer storage memory applications -- Design and Analysis of a CMOS 180 nm Fractional N Frequency Synthesizer -- Memristor based Approximate Adders for Error Resilient Applications -- Integrated Mems Capacitive Pressure Sensor with On-Chip CDC for a wide Operating Temperature Range -- A High SNDR and Wider Signal Bandwidth CT ∑∆ Modulator with a Single Loop Non-linear Feedback Compensation -- Design of Current Mode CNTFET Transceiver for Bundled Carbon Nanotube Interconnect -- Weak Cell Detection Techniques for Memristor Based Memories -- Enhancement of Transconductance using Multi-recycle Folded Cascode Amplifier -- Nondestructive Read Circuit for Memristor based Memories -- A Built in Self Repair Architecture for Random Access Memories -- A Current Mode DC-DC Boost Converter with Fast Transient and on-chip Current Sensing Technique -- A Modified GDI Based Low Power & High Read Stability 8T SRAM Memory with CNTFET Technology -- High Performance Trench Gate Power MOSFET of Indium Phosphide -- Memristor Equipped Error Detection Technique -- 28nm FD-SOI SRAM Design using Read Stable Bit Cell Architecture -- Design and Verification of Memory Controller with Host WISHBONE Interface -- 8-Bit Asynchronous Wave-Pipelined Arithmetic-Logic Unit.…”
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