APA (7th ed.) Citation

Taraate, V. (2019). Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog (1st ed. 2019.). Springer Nature Singapore. https://doi.org/10.1007/978-981-10-8776-9

Chicago Style (17th ed.) Citation

Taraate, Vaibbhav. Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog. 1st ed. 2019. Singapore: Springer Nature Singapore, 2019. https://doi.org/10.1007/978-981-10-8776-9.

MLA (9th ed.) Citation

Taraate, Vaibbhav. Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog. 1st ed. 2019. Springer Nature Singapore, 2019. https://doi.org/10.1007/978-981-10-8776-9.