Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog /

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrat...

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Detaylı Bibliyografya
Yazar: Taraate, Vaibbhav (Yazar)
Müşterek Yazar: SpringerLink (Online service)
Materyal Türü: e-Kitap
Dil:İngilizce
Baskı/Yayın Bilgisi: Singapore : Springer Nature Singapore : 2019.
Imprint: Springer,
Edisyon:1st ed. 2019.
Konular:
Electronic circuits.
Microprogramming .
Logic design.
Electronic Circuits and Systems.
Control Structures and Microprogramming.
Logic Design.
Online Erişim:Full-text access
Diğer Bilgiler
Özet:This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.
Fiziksel Özellikler:XXI, 307 p. 263 illus., 196 illus. in color. online resource.
ISBN:9789811087769
DOI:10.1007/978-981-10-8776-9

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