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High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliabilit...
| Main Authors: | , |
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| Corporate Author: | |
| Format: | e-Book |
| Language: | English |
| Published: |
Singapore :
Springer Nature Singapore :
2018.
Imprint: Springer, |
| Edition: | 1st ed. 2018. |
| Series: | Computer Architecture and Design Methodologies,
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| Subjects: | |
| Online Access: | Full-text access |
| Summary: | This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. . |
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| Physical Description: | XX, 197 p. 104 illus., 72 illus. in color. online resource. |
| ISBN: | 9789811010736 |
| ISSN: | 2367-3486 |
| DOI: | 10.1007/978-981-10-1073-6 |