Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog /

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrat...

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Bibliographic Details
Main Author: Taraate, Vaibbhav (Author)
Corporate Author: SpringerLink (Online service)
Format: e-Book
Language:English
Published: Singapore : Springer Nature Singapore : 2019.
Imprint: Springer,
Edition:1st ed. 2019.
Subjects:
Electronic circuits.
Microprogramming .
Logic design.
Electronic Circuits and Systems.
Control Structures and Microprogramming.
Logic Design.
Online Access:Full-text access
Table of Contents:
  • Introduction
  • SOC Design
  • RTL Design Guidelines
  • RTL Design and Verification
  • Processor cores and Architecture design
  • Buses and protocols in SOC designs
  • DSP Algorithms and Video Processing
  • ASIC and FPGA Synthesis
  • Static Timing Analysis
  • SOC Prototyping
  • SOC Prototyping guidelines
  • Design Integration and SOC synthesis
  • Interconnect delays and Timing
  • SOC Prototyping and debug techniques
  • Testing at the board level.

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